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 ALINT™ is a VHDL and Verilog Design Rule Checking Tool used to analyze HDL source code against a comprehensive set of ASIC design guidelines for early bug detection, cross-probing - VHDL IEEE 1076 (1987, 1993, 2002 and 2008), Verilog (1995, 2001, 2005) and Mixed Language Design analysis/rule checking
- STARC® VHDL Rule Library
- STARC® Verilog Rule Library
- Aldec VHDL and Verilog Basic Rules
- Custom policy & rule parameters
- Violation viewer & violation summary
- Cross-probing to source code
- Compare results between linting sessions
- Violation sorting & filtering
- Rule description viewer
- Ruleset editor
- Rule parameters viewer
- Policy editor
- Clock reset/auto-detection
- Synthesis emulation (netlist level)
- Gated clock handling
- Pattern matching (chip-level)
- Black box handling
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Product Entered: 2009-02-26,
Last Modified: 2010-02-21 |
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