|
|
|
 Riviera-PRO is a common-kernel, mixed language, multi-platform simulator for Verilog, SystemVerilog, VHDL, SystemC/C/C++, Assertions and EDIF - It supports System Level Verification
- Languages Supported: VHDL, Verilog® HDL, SystemVerilog IEEE 1800 Design, SystemVerilog IEEE 1800 (Verification), SystemC TM 2.2 IEEE 1666/OSCI 2.2, Mixed language & EDIF 200V
- Supported Platforms: Linux 32-bit, Linux 64-bit, Microsoft Windows, 2000/2003/XP/VISTA
- Design Entry and Design Management
- HDL and Text Editor
- Design Manager
- Maco/Tcl/Tk/Pearl script support
- Syntax highlighting and auto-complete
- HDL simulation
- Common Kernel, Mixed language HDL Simulator
- 64-Bit Multi-Threaded Design Environment
- Script compatible with other HDL simulators
- Verilog Simulation Performance Optimizations (RTL & Gate Level)
- Accelerated Waveform and List Viewer (ASDB)
- Waveform Compare
- Testbench Generator from Waveform/State Diagram
- Server Farm Manager- HDL Regressions
- Memory Viewer
- Advanced Dataflow Window
- Code Performance Profiler
- Statement/Branch/Expression/Toggle Coverage
- SystemC Simulation, C/C++ debugging in HDL
- Post Simulation Debugging
- Synopsys® SmartModels™, SWIFT™ Interface and LMTV
- DSP design and co-simulation with MATLAB®/Simulink®
- Assertions and Functional Coverage support
- Assertion and Cover Viewer
- Assertions and Covers in Waveform Viewer
- Code Coverage
- Set Breakpoints ALINT™ Lint – Design Rule Checking
- VHDL, Verilog and Mixed language design rule libraries
- Violation Manger
- Configuration Manger
- User defined rule properties
|
|
|
|
|
 |
Product Entered: 2009-02-26,
Last Modified: 2010-02-21 |
|
